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ISL97671A
TABLE 3A. ISL97671A REGISTER LISTING
DEFAULT
SMBUS/I 2 C
ADDRESS
0x00
REGISTER
PWM
BIT 7
BRT7
BIT 6
BRT6
BIT 5
BRT5
BIT 4
BRT4
BIT 3
BRT3
BIT 2
BRT2
BIT 1
BRT1
BIT 0
BRT0
VALUE
0xFF
PROTOCOL
Read and Write
Brightness
Control Register
0x01
Device Control
Reserved
Reserved
Reserved
Reserved
Reserved PWM_MD
PWM_SEL
BL_CTL
0x00
Read and Write
Register
0x02
Fault/Status
Reserved
Reserved
2_CH_SD
1_CH_SD
BL_STAT
OV_CURR
THRM_SHDN
FAULT
0x00
Read Only
Register
0x03
Identification
LED
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
0xC8
Read Only
Register
PANEL
0x07
DC Brightness
BRTDC7
BRTDC6
BRTDC5
BRTDC4
BRTDC3
BRTDC2
BRTDC1
BRTDC0
0xFF
Read and Write
Control Register
0x08
Configuration
Reserved
Reserved
Reserved
BstSlew
BstSlew
FSW
Reserved
VSC
0x1F
Read and Write
Register
Rate1
Rate0
0x09
Output Channel Reserved
Reserved
CH5
CH4
CH3
CH2
CH1
CH0
0x3F
Read and Write
Register
0x0A
Phase Shift Deg
Equal
Phase
Phase
Phase
Phase
Phase
Phase
Phase
0x00
Read and Write
Phase
Shift6
Shift5
Shift4
Shift3
Shift2
Shift1
Shift0
TABLE 3B. DATA BIT DESCRIPTIONS
ADDRESS
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x0A
REGISTER
PWM Brightness Control
Register
Device Control Register
Fault/Status Register
Identification Register
DC Brightness Control Register
Configuration Register
Output Channel Mask/Fault
Readout Register
Phase Shift Degree
19
DATA BIT DESCRIPTIONS
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
PWM_MD, PWM_SEL: select the dimming method - see Table 4 for more details. Default = 00
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
LED PANEL = 1
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
BRTDC[7..0] = 256 steps of DC brightness control
BstSlewRate[1..0] = Controls strength of FET driver. 00 - 25% drive strength, 01 - 50% drive strength,
10 - 75% drive strength, 11 - 100% drive strength.
F SW = Switching frequencies selection, F SW = 0 = 1.2MHz. F SW = 1 = 600kMHz
VSC[0] = Short circuit thresholds selection, 0 = disabled, 1 = 7.2V minimum
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In
Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled
EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of
channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is
PhaseShift<6:0>/12.8MHz.
FN7709.3
November 30, 2012
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